A bistable digital circuit, such as a flip flop, stores data by using two stable equilibrium states to represent 1 and 0. All bistable circuits have a metastable equilibrium state in between the two stable states. This metastable state is encountered during the transition from one stable state to the other stable state. FIG. 1 is a graphical representation of the transition from one stable state to another stable state through a metastable state. Although it is theoretically possible for a circuit to stay in this metastable state indefinitely, in practice, the duration of the metastable state is short. The existence of this metastable equilibrium state means the conceptually binary flip flop may actually be in a third undefined state for an indefinite amount of time. This ambiguity can lead to random failures in digital systems where only 1s and 0s are expected.
Over 35 years ago, random mysterious failures in early digital electronic systems led to the discovery of metastable behavior in flip flops and the conditions under which metastable behavior are exhibited. Metastability often occurs when flip flops have asynchronous inputs and the asynchronous inputs violate the setup and hold conditions of the flip flops. For example, a common type of flip flop is the D flip flop. One variation of this flip flop has a data input, a clock input and a data output. On the rising edge of the clock input, the data input is sampled and stored in the flip flop. The data output changes after a delay to reflect the stored data. However, for the D flip flop to function as described, the data input must be stable for some period of time before the rising clock edge appears, and remain stable for some period of time after the rising clock edge passes. The period of time before the appearance of the rising clock edge is called the setup time. The period of time after the rising clock edge passes is called the hold time. FIG. 2 illustrates the D flip flop setup and hold times. If the data input is not stable during the setup and hold time, a condition known as a setup and hold violation, the flip flop may go into a metastable state and the data output will not be a 1 or a 0 as desired.
An asynchronous input signal is a signal which may arrive at any moment. The signal has no defined time relationship relative to the clock of the receiving flip flop. Asynchronous signals commonly occur in systems with multiple clocks. A signal may be generated in one clock domain and be transmitted to another clock domain. If the source clock and the destination clock have no fixed relationship, then the signal will arrive randomly from the perspective of the destination clock domain. Given this random arrival, the asynchronous signal will frequently not be stable during the setup and hold periods of the receiving flip flop.
A common example of a system with multiple clocks is a communication network where a stream of data bits with an embedded clock arrives at a switch. The data and recovered clock constitute a clock domain which is separate from the clock domain of the switch. The two clock domains are often independent of each other. The input data must cross into the switch clock domain for examination in order to determine its next destination. The data may then have to cross into a third clock domain for transmission out of the switch at a different bit rate to another switch.
Another example of a system with multiple clocks is in large semiconductor chips. Large chips are composed of groups of circuits which are often called modules or cores. Modules send and receive signals from other modules that may be clocked by different clocks from that of the sender. Thus, each module may constitute a separate and independent clock domain. While clocks within a module are typically distributed to the flip flops of the chip with low skew, chip sizes have grown so large that process, voltage, and temperature (“PVT”) variations across the chip make low skew clock distribution across the entire chip impossible. Thus, even modules clocked by the same frequency clocks may have unknown phase relationships between the sending and receiving clocks. Signals between such modules must then be viewed as asynchronous signals.
The increasing expectations for reliable system operation, the increasing size of semiconductor chips, the prevalence of multiple clocks, the increasing clock frequencies and the amount of logic all join to make the prevention of metastability in flip flops a basic consideration in semiconductor chip design.